1. Field of the Invention
The invention relates generally to high speed electronic processors and, more particularly, to an electronic processor configured in a parallel architecture.
2. Description of the Relevant Art
The need for a processor able to perform complex mathematical operations on multidimensional data arrays is greatly needed in many scientific fields such as, for example, seismic processing, signal processing, and numerical analysis.
Various mathematical processors exist that have the capability of performing mathematical floating point operations at very high computational rates. In practice, these machines generally do not compute at this high rate while processing arrays of data due to a phenomenon known as "I/O bottleneck."
In a typical computational problem, the data array is stored in an addressable main memory unit. The data in the array must first be fetched from the main memory and routed to the mathematical processor prior to processing. The results of the processor operations must then be routed back to the main memory and stored. These steps of fetching, routing, and storing are generally performed sequentially and are performed at a data I/O rate that is much lower than the computational rate of the processor.
Further, existing high speed mathematical processors generally operate on vectors, i.e., one dimensional sets of points in the data array, during a processing cycle. The data array is composed of a multitude of vectors. Thus, many sequential I/O operations must be performed to retrieve the required vectors from the array, to route these vectors to the mathematical processor, and to store the resultant vectors in the main memory unit.
Accordingly, a high speed mathematical processor that is designed to reduce the I/O bottleneck is greatly needed in many technical disciplines.